Today at <a href="http://sandbox.arrayfire.com/arrayfire-at-sc15/">SuperComputing 2015</a>, ArrayFire demonstrated its first FPGA-accelerated application running on a Xilinx FPGA using OpenCL. In May 2015, <a href="http://press.xilinx.com/2015-05-26-New-Release-of-the-SDAccel-Development-Environment-Accelerates-Data-Center-Applications-with-Expanded-Ecosystem-of-Platforms-Libraries-and-Design-Services">ArrayFire became a Xilinx Alliance member</a> which provided us early access to the <a href="http://www.xilinx.com/products/design-tools/software-zone/sdaccel.html">Xilinx SDAccel Development Environment</a> within initial support for OpenCL.

Over the last few months, we implemented several programs for the FPGA and subsequently learned a lot about optimizing OpenCL kernels to take advantage of pipelining, wide memory busses, and the various forms of configurable local memory offered on Xilinx hardware.

Our first fully ported application is from computer vision: the <a href="http://www.springerlink.com/index/10.1007/11744023">FAST</a> feature extractor. We'll include more details later, but for now I've included a screenshot below. To see it in action stop by booth 2229 at SC15!
<a href="http://sandbox.arrayfire.com/wp-content/uploads/2015/11/snapshot12.png"><img class="aligncenter size-large wp-image-8687" src="http://sandbox.arrayfire.com/wp-content/uploads/2015/11/snapshot12-1024x609.png" alt="FAST on a Xilinx FPGA" width="742" height="441" /></a>