<a href="http://newsroom.intel.com/community/intel_newsroom/bios?n=Stephen%20S.%20Pawlowski&amp;f=searchAll">Stephen Pawlowski</a> of Intel gave an interesting keynote today at <a href="http://www.isc-events.com/isc13">ISC 2013</a>. He continued the theme of <a href="http://blog.accelereyes.com/blog/2013/06/17/isc-2013-keynote-by-bill-dally-of-nvidia/">yesterday's keynote</a> to address challenges our market faces in getting to exascale computing. Here is a summary of the points he made during his talk:
<ul>
	<li>Getting to exascale by 2020 requires performance improvement of 2x every year</li>
	<li>Innovations anticipated include stacked chips and optical layers</li>
	<li>DRAM is not scaling with Moore's Law</li>
	<li>More power goes into transferring data than in computing</li>
	<li>Need to operate transistors near threshold</li>
	<li>New materials for DRAM needed. Resistive memory could replace DRAM.</li>
	<li>Need to explore both the big die and the small die paths as we approach 2020
<ul>
	<li>Big die path leads to 10 billion transistors on a die</li>
	<li>Small die path entails fewer transistors on a small cost effective die</li>
</ul>
</li>
</ul>
It is clear that Intel is thinking hard about the challenges facing the processor industry and exploring many simultaneous paths to push the market forward.

We look forward to finding the video and slides of Stephen Pawlowski’s keynote posted online, and we’ll provide a link to that information when it is posted by Intel and the ISC 2013 coordinators.

If you are at ISC 2013, you can find us demoing in NVIDIA’s booth #220 near the exhibition entryway.

&nbsp;
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